This invention relates to user-configurable multiprocessor computational systems having ultra-scalar single-type computational logic.
Developing new computational processor systems for continuously changing application requirements has a primary architectural problem of tradeoff between user selectivity for high specialization efficiency and general-purpose use with lower efficiency. General-purpose processors like the well-known Pentium, PowerPC and Alpha can perform any algorithm that is programmed adequately for using their respectively generalized instruction sets. They can not obtain the performance efficiency, accuracy and speed of application-specific integrated circuits (ASIC) that are developed for specific applications and which implement only the functions that are required to run a dedicated specific task. ASIC structure having computational algorithm generally adequate for a particular application task can be small, less expensive and yet faster than a general-purpose programmable microprocessor. For example, a special graphic module for a PC can accelerate a process of drawing graphical primitives ten-to-twenty times the process speed of a general-purpose processor, but is efficient for one specific computational task only. Any alteration of the task or its conditions makes the ASIC totally useless.
It is not economically feasible to develop ASICs for a vastness of range of applications that is increasing continuously. The conventional solution for achieving ASIC advantages is to construct electronically huge general-purpose microprocessors that have pluralities of separate computational units which can be programmed by a computer manufacturer to function like a specialized ASIC. Each separate conventional computational unit is an oversized, slow and expensive general-purpose microprocessor that is known as a field-programmable gate array (FPGA).
In conventional FPGA architecture, manufacturers construct dedicated smallness efficiency from general-purpose largeness inefficiency. A huge manufacturer-specialized FPGA becomes an ASIC-substitute FPGA that requires massive chip silicon to achieve genuine small ASIC objectives. In addition to orders of magnitude of excess silicon, there is comparable waste of in-and-out computational time with ASIC-substitute FPGAs.
By contrast with this invention, instead of requiring massive excesses of computer-chip silicon and time lag for each of many manufacturer-specialized ASIC-substitute FPGAs, a dynamically reconfigurable microprocessor has been described by the present inventor in a prior patent application having Ser. No. 09/088,165, filed Jun. 1, 1998. In addition to that invention, this invention by the same inventor provides architecture and computational method for further speeding and adapting computer processing.
With dynamic reconfiguration, a user instead of a manufacturer can configure and reconfigure one or a small plurality of microprocessors to accomplish what previously required large pluralities of manufacturer-configured FPGAs or many more ASICs.
Added to dynamic reconfiguration by this invention are higher computational speed, smaller-yet chip size, greater computational adaptivity, greater programmable adaptivity and more "computer-centric" adaptivity.